I. Field of the Disclosure
The technology of the present application relates generally to magnetic tunnel junctions (MTJ), related methods, and use of a MTJ in magnetic random access memory (MRAM).
II. Background
Magnetic random access memory (MRAM) is non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ). MRAM is advantageous, because a MTJ can be used to store information even when power is turned off. Data is stored in the MTJ as a small magnetic element rather than an electric charge or current. An exemplary MTJ 10 is illustrated in FIG. 1. Data is stored in the MTJ 10 according to the magnetic orientation between two layers: a free layer 12 disposed above a fixed or pinned layer 14. The free and pinned layers 12, 14 are formed from a ferromagnetic material. The MTJ 10 is configured in a conventional “bottom-spin valve” configuration wherein the pinned layer 14 is disposed below the free layer 12. The free and pinned layers 12, 14 are separated by a tunnel junction or barrier 16 formed by a thin non-magnetic dielectric layer. The free and pinned layers 12, 14 can store information even when the magnetic H-field is ‘0’ due to the hysteresis loop 18 of the MTJ 10. Electrons can tunnel through the tunnel barrier 16 if a bias voltage is applied between two electrodes 20, 22 coupled on ends of the MTJ 10. The tunneling current depends on the relative orientation of the free and pinned layers 12, 14. When using a spin-torque-transfer (STT) MTJ, the difference in the tunneling current as the spin alignment of the free and pinned layers is switched between P and AP is known as the tunnel magnetoresistance ratio (TMR).
When the magnetic orientation of the free and pinned layers 12, 14 are anti-parallel (AP) to each other (shown in FIG. 1 as MTJ 10′), a first memory state exists (e.g., a logical ‘1’). When the magnetic orientation of the free and pinned layers 12, 14 are parallel (P) to each other (shown in FIG. 1 as MTJ 10″), a second memory state exists (e.g., a logical ‘0’). The magnetic orientation of the free and pinned layers 12, 14 can be sensed to read data stored in the MTJ 10 by sensing the resistance when current flows through the MTJ 10. Data can also be written and stored in the MTJ 10 by applying a magnetic field to change the orientation of a free ferromagnetic layer 12 to either a P or AP magnetic orientation with respect to the pinned layer 14. The magnetic orientation of the free layer 12 can be changed, but the magnetic orientation of the pinned layer 14 is fixed.
FIG. 2 illustrates a STT MTJ 23 (referred to as “MTJ 23”) of similar design to the MTJ 10 in FIG. 1. The MTJ 23 is provided as part of a MRAM bitcell 24 to store non-volatile data. The MRAM bitcell 24 may be provided in a memory array and used as memory storage for any type of system requiring electronic memory, such as a computer processing unit (CPU) or processor-based system, as examples. A metal-oxide semiconductor (typically n-type MOS, i.e., NMOS) access transistor 26 is provided to control reading and writing to the MTJ 23. The drain (D) of the access transistor 26 is coupled to the bottom electrode 22 of the MTJ 23, coupled to the pinned layer 14. A write line (VWL) is coupled to the gate (G) of the access transistor 26. The source (S) of the access transistor 26 is coupled to a voltage source (VS). A bit line (VBL) is coupled to the top electrode 20 of the MTJ 23, which is coupled to the free layer 12.
When reading data stored in the MTJ 23, the bit line (VBL) is activated for the access transistor 26 to allow current to flow through the MTJ 23 between the electrodes 20, 22. A low resistance, as measured by voltage applied on the bit line (VBL) divided by the measured current, is associated with a P orientation between the free and pinned layers 12, 14. A higher resistance is associated with an AP orientation between the free and pinned layers 12, 14. When writing data to the MTJ 23, the gate (G) of the access transistor 26 is activated by activating the write line (VWL). A voltage differential between the bit line (VBL) and the source line (VS) is applied. As a result, a write current (I) is generated between the drain (D) and the source (S). If the magnetic orientation is to be changed from AP to P, a write current (IAP-P) flowing from the top electrode 20 to the bottom electrode 22 is generated, which induces a spin transfer torque (STT) at the free layer 12 to change the magnetic orientation of the free layer 12 to P with respect to the pinned layer 14. If the magnetic orientation is to be changed from P to AP, a current (IP-AP) flowing from the bottom electrode 22 to the top electrode 20 is produced, which induces an STT at the free layer 12 to change the magnetic orientation of the free layer 12 to AP with respect to the pinned layer 14.
As illustrated in FIG. 2, more write current (I) can be supplied by the circuitry to switch the MTJ 23 in the MRAM bitcell 24 from an AP to P state (IAP-P) than from a P to AP state (IP-AP). This is due to the source loading of the access transistor 26 in the MRAM bitcell 24. The source loading of the access transistor 26 has the effect of providing more write current (I) to switch the MTJ 23 from an AP to P state than from a P to AP state. However, the inherent magnetic characteristics of MTJ 23 require the opposite. That is, when the MTJ 23 is employed in the MRAM bitcell 24, as illustrated in FIG. 2, more write current (I) is required to switch the MTJ 23 from a P to AP state than from an AP to P state. This is shown by the graph 30 in FIG. 3, which illustrates the inherent magnetic characteristics of the MTJ 23 as a function of write current (IC). As shown therein, the amount of write current (I) required to switch the MTJ 23 from a P to AP state (IC P-AP) is much greater than the amount of write current (I) required to switch the MTJ 23 from an AP to P state (IC AP-P). This presents a design conflict. On the one hand, the inherent magnetic characteristics of the MTJ 23 requires more write current (I) to switch the MTJ 23 from a P to AP state than from an AP to P state. However, when the MTJ 23 is employed in the MRAM bitcell 24, more write current (I) can be supplied by the circuitry to switch the MTJ 23 from an AP to P state than from a P to AP state.
In summary, as a result of this design conflict, the inherent write current characteristics of the MTJ 23 are not aligned to the write supply current capability of the MTJ 23 when employed in the MRAM bitcell 24. More write current is required to switch the MTJ 23 from a P to AP state when employed in the MRAM bitcell 24. However, the MRAM bitcell 24 can provide more write current to switch the MTJ 23 from an AP to P state. Thus, a need exists to provide a MTJ design that solves this design conflict. More efficient switching of memory states in circuits and/or applications employing MRAM may be realized as a result.